Multiplication is arguably the most cost-dominant operation in modern deep neural networks (DNNs), limiting their achievable efficiency and thus more extensive deployment in resource-constrained applications. To tackle this limitation, pioneering works have developed handcrafted multiplication-free DNNs, which require expert knowledge and time-consuming manual iteration, calling for fast development tools. To this end, we propose a Neural Architecture Search and Acceleration framework dubbed NASA, which enables automated multiplication-reduced DNN development and integrates a dedicated multiplication-reduced accelerator for boosting DNNs' achievable efficiency. Specifically, NASA adopts neural architecture search (NAS) spaces that augment the state-of-the-art one with hardware-inspired multiplication-free operators, such as shift and adder, armed with a novel progressive pretrain strategy (PGP) together with customized training recipes to automatically search for optimal multiplication-reduced DNNs; On top of that, NASA further develops a dedicated accelerator, which advocates a chunk-based template and auto-mapper dedicated for NASA-NAS resulting DNNs to better leverage their algorithmic properties for boosting hardware efficiency. Experimental results and ablation studies consistently validate the advantages of NASA's algorithm-hardware co-design framework in terms of achievable accuracy and efficiency tradeoffs. Codes are available at https://github.com/GATECH-EIC/NASA.

就起搏器提供的信号（即，神心电图电测（EGM））和信号医生使用（即12-铅心电图（ECG））而言，存在差距以诊断出异常节律。因此，前者，即使远程传输，医生也不足以提供精确的诊断，更不用说更及时干预。为了缩短这种差距，并对即时响应不规则和不频繁的心室节律的即时反应进行启发式步骤，我们提出了一个新的框架被称为RT-RCG，以自动搜索（1）高效的深神经网络（DNN）结构和然后（2）相应的加速器，能够实现来自EGM信号的ECG信号的实时和高质量的重建。具体地，RT-RCG提出了一种针对EGM信号的ECG重建量身定制的新的DNN搜索空间，并结合了可分辨率的加速搜索（DAS）发动机，以有效地导航大而离散的加速器设计空间以产生优化的加速器。各种环境下的广泛实验和消融研究一致地验证了RT-RCG的有效性。据我们所知，RT-RCG是第一个利用神经结构搜索（NAS）来同时解决重建效能和效率的效率。

具有密集乘法的神经网络（NNS）（例如，卷积和变形金刚）具有饥饿的能力，阻碍了它们更广泛的部署到资源受限的设备中。因此，遵循节能硬件实施的共同实践的无乘法网络，以更有效的运算符（例如，位移位和加法）参数化NN，并引起了人们的关注。但是，从实现的准确性方面，无乘法网络的表现不足。为此，这项工作倡导混合NN，包括强大但昂贵的乘法和有效而强大的运营商来嫁给两全其美的运营商，并提出了ShiftAddnas，它们可以自动寻找更准确，更有效的NN。我们的ShiftAddnas突出了两个推动者。具体而言，它集成了（1）第一个混合搜索空间，该空间同时结合了基于乘法的和无乘法的运算符，以促进精确和有效的混合NNS的开发； （2）一种新型的重量共享策略，可以在遵循异质分布的不同操作员之间有效分享（例如，用于卷积的高斯与添加操作员的拉普拉斯人），并同时导致超级降低的超网尺寸和更好的搜索网络。对各种模型，数据集和任务的广泛实验和消融研究始终如一地验证了ShiftAddnas的功效，例如，与最先进的NN相比，获得的精度高达 +4.7％，或者+4.9更好的BLEU得分，而BLEU得分更好最多可提供93％或69％的能源和延迟节省。可以在https://github.com/rice-eic/shiftaddnas上获得代码和预估计的模型。

深神经网络（DNNS）在各种机器学习（ML）应用程序中取得了巨大成功，在计算机视觉，自然语言处理和虚拟现实等中提供了高质量的推理解决方案。但是，基于DNN的ML应用程序也带来计算和存储要求的增加了很多，对于具有有限的计算/存储资源，紧张的功率预算和较小形式的嵌入式系统而言，这尤其具有挑战性。挑战还来自各种特定应用的要求，包括实时响应，高通量性能和可靠的推理准确性。为了应对这些挑战，我们介绍了一系列有效的设计方法，包括有效的ML模型设计，定制的硬件加速器设计以及硬件/软件共同设计策略，以启用嵌入式系统上有效的ML应用程序。

深度神经网络（DNN）的记录断裂性能具有沉重的参数化，导致外部动态随机存取存储器（DRAM）进行存储。 DRAM访问的禁用能量使得在资源受限的设备上部署DNN是不普遍的，呼叫最小化重量和数据移动以提高能量效率。我们呈现SmartDeal（SD），算法框架，以进行更高成本的存储器存储/访问的较低成本计算，以便在推理和培训中积极提高存储和能量效率。 SD的核心是一种具有结构约束的新型重量分解，精心制作以释放硬件效率潜力。具体地，我们将每个重量张量分解为小基矩阵的乘积以及大的结构稀疏系数矩阵，其非零被量化为-2的功率。由此产生的稀疏和量化的DNN致力于为数据移动和重量存储而大大降低的能量，因为由于稀疏的比特 - 操作和成本良好的计算，恢复原始权重的最小开销。除了推理之外，我们采取了另一次飞跃来拥抱节能培训，引入创新技术，以解决培训时出现的独特障碍，同时保留SD结构。我们还设计专用硬件加速器，充分利用SD结构来提高实际能源效率和延迟。我们在不同的设置中对多个任务，模型和数据集进行实验。结果表明：1）应用于推理，SD可实现高达2.44倍的能效，通过实际硬件实现评估; 2）应用于培训，储存能量降低10.56倍，减少了10.56倍和4.48倍，与最先进的训练基线相比，可忽略的准确性损失。我们的源代码在线提供。

图表卷积网络（GCNS）已成为最先进的图形学习模型。但是，它可以令人难以置于大图数据集的推断GCNS，这会将其应用于大型实际图表并阻碍更深层更复杂的GCN图形的探讨。这是因为真实世界图可能非常大而稀疏。此外，GCN的节点度倾向于遵循幂律分布，因此具有高度不规则的邻接矩阵，导致数据处理和移动中的禁止低效率，从而显着地限制了可实现的GCN加速效率。为此，本文提出了一种GCN算法和加速器协同设计框架被称为GCOD，其在很大程度上可以缓解上述GCN不规则性并提高GCNS推理效率。具体地，在算法级别上，GCOD集成了分割和征服GCN训练策略，该训练策略将图形偏离在本地邻域中的密集或稀疏，而不会影响模型精度，从而导致（主要）的图形邻接矩阵仅仅是两个级别的工作量并享受大部分增强的规律性，从而轻松加速。在硬件水平上，我们进一步开发了一个具有分离发动机的专用双子加速器，以处理每个上述密集和稀疏工作负载，进一步提高整体利用率和加速效率。广泛的实验和消融研究验证了我们的GCOD始终如一地减少了与CPU，GPU和现有技术GCN加速器相比的15286倍，294倍，7.8倍和2.5倍的加速，包括HYGCN和AWB -GCN分别在保持甚至提高任务准确性的同时。

Vision Transformers (ViTs) have achieved state-of-the-art performance on various vision tasks. However, ViTs' self-attention module is still arguably a major bottleneck, limiting their achievable hardware efficiency. Meanwhile, existing accelerators dedicated to NLP Transformers are not optimal for ViTs. This is because there is a large difference between ViTs and NLP Transformers: ViTs have a relatively fixed number of input tokens, whose attention maps can be pruned by up to 90% even with fixed sparse patterns; while NLP Transformers need to handle input sequences of varying numbers of tokens and rely on on-the-fly predictions of dynamic sparse attention patterns for each input to achieve a decent sparsity (e.g., >=50%). To this end, we propose a dedicated algorithm and accelerator co-design framework dubbed ViTCoD for accelerating ViTs. Specifically, on the algorithm level, ViTCoD prunes and polarizes the attention maps to have either denser or sparser fixed patterns for regularizing two levels of workloads without hurting the accuracy, largely reducing the attention computations while leaving room for alleviating the remaining dominant data movements; on top of that, we further integrate a lightweight and learnable auto-encoder module to enable trading the dominant high-cost data movements for lower-cost computations. On the hardware level, we develop a dedicated accelerator to simultaneously coordinate the enforced denser/sparser workloads and encoder/decoder engines for boosted hardware utilization. Extensive experiments and ablation studies validate that ViTCoD largely reduces the dominant data movement costs, achieving speedups of up to 235.3x, 142.9x, 86.0x, 10.1x, and 6.8x over general computing platforms CPUs, EdgeGPUs, GPUs, and prior-art Transformer accelerators SpAtten and Sanger under an attention sparsity of 90%, respectively.

深度学习技术在各种任务中都表现出了出色的有效性，并且深度学习具有推进多种应用程序（包括在边缘计算中）的潜力，其中将深层模型部署在边缘设备上，以实现即时的数据处理和响应。一个关键的挑战是，虽然深层模型的应用通常会产生大量的内存和计算成本，但Edge设备通常只提供非常有限的存储和计算功能，这些功能可能会在各个设备之间差异很大。这些特征使得难以构建深度学习解决方案，以释放边缘设备的潜力，同时遵守其约束。应对这一挑战的一种有希望的方法是自动化有效的深度学习模型的设计，这些模型轻巧，仅需少量存储，并且仅产生低计算开销。该调查提供了针对边缘计算的深度学习模型设计自动化技术的全面覆盖。它提供了关键指标的概述和比较，这些指标通常用于量化模型在有效性，轻度和计算成本方面的水平。然后，该调查涵盖了深层设计自动化技术的三类最新技术：自动化神经体系结构搜索，自动化模型压缩以及联合自动化设计和压缩。最后，调查涵盖了未来研究的开放问题和方向。

随着机器学习和系统社区努力通过自定义深度神经网络（DNN）加速器，多样的精度或量化水平以及模型压缩技术来实现更高的能源效率，因此需要设计空间探索框架，以结合量化意识的处理。在具有准确和快速的功率，性能和区域模型的同时，进入加速器设计空间。在这项工作中，我们提出了Quidam，这是一种高度参数化的量化量化DNN加速器和模型共探索框架。我们的框架可以促进对DNN加速器设计空间探索的未来研究，以提供各种设计选择，例如位精度，处理元素类型，处理元素的刮擦大小，全局缓冲区大小，总处理元素的数量和DNN配置。我们的结果表明，不同的精确度和处理元素类型会导致每个区域和能量性能方面的显着差异。具体而言，我们的框架标识了广泛的设计点，其中每个面积和能量的性能分别差异超过5倍和35倍。通过拟议的框架，我们表明，与最佳基于INT16的实施相比，轻巧的处理元素可在准确性结果上实现，每个区域的性能和能源改善高达5.7倍。最后，由于预先特征的功率，性能和区域模型的效率，Quidam可以将设计勘探过程加快3-4个数量级，因为它消除了每种设计的昂贵合成和表征的需求。

Designing accurate and efficient ConvNets for mobile devices is challenging because the design space is combinatorially large. Due to this, previous neural architecture search (NAS) methods are computationally expensive. ConvNet architecture optimality depends on factors such as input resolution and target devices. However, existing approaches are too resource demanding for case-by-case redesigns. Also, previous work focuses primarily on reducing FLOPs, but FLOP count does not always reflect actual latency. To address these, we propose a differentiable neural architecture search (DNAS) framework that uses gradient-based methods to optimize Con-vNet architectures, avoiding enumerating and training individual architectures separately as in previous methods. FBNets (Facebook-Berkeley-Nets), a family of models discovered by DNAS surpass state-of-the-art models both designed manually and generated automatically. FBNet-B achieves 74.1% top-1 accuracy on ImageNet with 295M FLOPs and 23.1 ms latency on a Samsung S8 phone, 2.4x smaller and 1.5x faster than MobileNetV2-1.3[17] with similar accuracy. Despite higher accuracy and lower latency than MnasNet[20], we estimate FBNet-B's search cost is 420x smaller than MnasNet's, at only 216 GPUhours. Searched for different resolutions and channel sizes, FBNets achieve 1.5% to 6.4% higher accuracy than Mo-bileNetV2. The smallest FBNet achieves 50.2% accuracy and 2.9 ms latency (345 frames per second) on a Samsung S8. Over a Samsung-optimized FBNet, the iPhone-Xoptimized model achieves a 1.4x speedup on an iPhone X. FBNet models are open-sourced at https://github. com/facebookresearch/mobile-vision. * Work done while interning at Facebook.… Figure 1. Differentiable neural architecture search (DNAS) for ConvNet design. DNAS explores a layer-wise space that each layer of a ConvNet can choose a different block. The search space is represented by a stochastic super net. The search process trains the stochastic super net using SGD to optimize the architecture distribution. Optimal architectures are sampled from the trained distribution. The latency of each operator is measured on target devices and used to compute the loss for the super net.

Recently, automated co-design of machine learning (ML) models and accelerator architectures has attracted significant attention from both the industry and academia. However, most co-design frameworks either explore a limited search space or employ suboptimal exploration techniques for simultaneous design decision investigations of the ML model and the accelerator. Furthermore, training the ML model and simulating the accelerator performance is computationally expensive. To address these limitations, this work proposes a novel neural architecture and hardware accelerator co-design framework, called CODEBench. It is composed of two new benchmarking sub-frameworks, CNNBench and AccelBench, which explore expanded design spaces of convolutional neural networks (CNNs) and CNN accelerators. CNNBench leverages an advanced search technique, BOSHNAS, to efficiently train a neural heteroscedastic surrogate model to converge to an optimal CNN architecture by employing second-order gradients. AccelBench performs cycle-accurate simulations for a diverse set of accelerator architectures in a vast design space. With the proposed co-design method, called BOSHCODE, our best CNN-accelerator pair achieves 1.4% higher accuracy on the CIFAR-10 dataset compared to the state-of-the-art pair, while enabling 59.1% lower latency and 60.8% lower energy consumption. On the ImageNet dataset, it achieves 3.7% higher Top1 accuracy at 43.8% lower latency and 11.2% lower energy consumption. CODEBench outperforms the state-of-the-art framework, i.e., Auto-NBA, by achieving 1.5% higher accuracy and 34.7x higher throughput, while enabling 11.0x lower energy-delay product (EDP) and 4.0x lower chip area on CIFAR-10.

混合精确的深神经网络达到了硬件部署所需的能源效率和吞吐量，尤其是在资源有限的情况下，而无需牺牲准确性。但是，不容易找到保留精度的最佳每层钻头精度，尤其是在创建巨大搜索空间的大量模型，数据集和量化技术中。为了解决这一困难，最近出现了一系列文献，并且已经提出了一些实现有希望的准确性结果的框架。在本文中，我们首先总结了文献中通常使用的量化技术。然后，我们对混合精液框架进行了彻底的调查，该调查是根据其优化技术进行分类的，例如增强学习和量化技术，例如确定性舍入。此外，讨论了每个框架的优势和缺点，我们在其中呈现并列。我们最终为未来的混合精液框架提供了指南。

语义细分是计算机视觉中的一个流行研究主题，并且在其上做出了许多努力，结果令人印象深刻。在本文中，我们打算搜索可以实时运行此问题的最佳网络结构。为了实现这一目标，我们共同搜索深度，通道，扩张速率和特征空间分辨率，从而导致搜索空间约为2.78*10^324可能的选择。为了处理如此大的搜索空间，我们利用差异架构搜索方法。但是，需要离散地使用使用现有差异方法搜索的体系结构参数，这会导致差异方法找到的架构参数与其离散版本作为体系结构搜索的最终解决方案之间的离散差距。因此，我们从解决方案空间正则化的创新角度来缓解离散差距的问题。具体而言，首先提出了新型的解决方案空间正则化（SSR）损失，以有效鼓励超级网络收敛到其离散。然后，提出了一种新的分层和渐进式解决方案空间缩小方法，以进一步实现较高的搜索效率。此外，我们从理论上表明，SSR损失的优化等同于L_0-NORM正则化，这说明了改善的搜索评估差距。综合实验表明，提出的搜索方案可以有效地找到最佳的网络结构，该结构具有较小的模型大小（1 m）的分割非常快的速度（175 fps），同时保持可比较的精度。

有效的深层神经网络（DNN）模型配备了紧凑的操作员（例如，深度卷积）在降低DNN的理论复杂性（例如，权重/操作总数）的同时，在保持体面的模型准确性的同时，显示出很大的潜力。但是，由于其通常采用的紧凑型操作员的低硬件利用率，现有的有效DNN仍然受到履行其提高现实硬件效率的承诺的限制。在这项工作中，我们为开发真实硬件有效的DNN开辟了新的压缩范式，从而提高了硬件效率，同时保持模型的准确性。有趣的是，我们观察到，尽管某些DNN层的激活功能有助于DNNS的训练优化和可实现的准确性，但在训练后可以正确删除它们，而不会损害模型的准确性。受到这一观察的启发，我们提出了一个称为DepthShrinker的框架，该框架通过缩小现有有效DNN的基本构建块来开发硬件友好的紧凑型网络，这些构件具有不规则的计算模式，并具有大量改进的硬件利用率，从而将硬件的计算模式缩小到密集的情况下。令人兴奋的是，我们的DepthShrinker框架提供了硬件友好的紧凑网络，既优于最先进的有效DNN和压缩技术方法元元素。我们的代码可在以下网址找到：https：//github.com/facebookresearch/depthshrinker。

While machine learning is traditionally a resource intensive task, embedded systems, autonomous navigation, and the vision of the Internet of Things fuel the interest in resource-efficient approaches. These approaches aim for a carefully chosen trade-off between performance and resource consumption in terms of computation and energy. The development of such approaches is among the major challenges in current machine learning research and key to ensure a smooth transition of machine learning technology from a scientific environment with virtually unlimited computing resources into everyday's applications. In this article, we provide an overview of the current state of the art of machine learning techniques facilitating these real-world requirements. In particular, we focus on deep neural networks (DNNs), the predominant machine learning models of the past decade. We give a comprehensive overview of the vast literature that can be mainly split into three non-mutually exclusive categories: (i) quantized neural networks, (ii) network pruning, and (iii) structural efficiency. These techniques can be applied during training or as post-processing, and they are widely used to reduce the computational demands in terms of memory footprint, inference speed, and energy efficiency. We also briefly discuss different concepts of embedded hardware for DNNs and their compatibility with machine learning techniques as well as potential for energy and latency reduction. We substantiate our discussion with experiments on well-known benchmark datasets using compression techniques (quantization, pruning) for a set of resource-constrained embedded systems, such as CPUs, GPUs and FPGAs. The obtained results highlight the difficulty of finding good trade-offs between resource efficiency and predictive performance.

Uniform-precision neural network quantization has gained popularity since it simplifies densely packed arithmetic unit for high computing capability. However, it ignores heterogeneous sensitivity to the impact of quantization errors across the layers, resulting in sub-optimal inference accuracy. This work proposes a novel neural architecture search called neural channel expansion that adjusts the network structure to alleviate accuracy degradation from ultra-low uniform-precision quantization. The proposed method selectively expands channels for the quantization sensitive layers while satisfying hardware constraints (e.g., FLOPs, PARAMs). Based on in-depth analysis and experiments, we demonstrate that the proposed method can adapt several popular networks channels to achieve superior 2-bit quantization accuracy on CIFAR10 and ImageNet. In particular, we achieve the best-to-date Top-1/Top-5 accuracy for 2-bit ResNet50 with smaller FLOPs and the parameter size.

深度神经网络（DNN）的算法 - 硬件共同设计的最新进展已经证明了它们在自动设计神经架构和硬件设计方面的潜力。然而，由于昂贵的培训成本和耗时的硬件实现，这仍然是一个充满挑战的优化问题，这使得对神经结构和硬件设计难以解答的巨大设计空间探索。在本文中，我们证明我们所提出的方法能够在帕累托前沿定位设计。这种功能由新颖的三相协同设计框架启用，具有以下新功能：（a）从硬件架构和神经结构的设计空间探索的DNN培训解耦，（b）提供硬件友好的神经结构空间通过考虑构造搜索单元的硬件特征，（c）采用高斯过程来预测准确性，延迟和功耗以避免耗时的合成和路由过程。与手动设计的Resnet101，Inceptionv2和MobileNetv2相比，我们可以在想象网数据集中获得高达3倍的准确度，高达5％的准确性。与其他最先进的共同设计框架相比，我们发现的网络和硬件配置可以达到更高的2％〜6％，精度为2倍〜26倍，延迟较高8.5倍。

Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems.This article aims to provide a comprehensive tutorial and survey about the recent advances towards the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic co-designs, being proposed in academia and industry.The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the trade-offs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

可微分的架构搜索逐渐成为神经结构中的主流研究主题，以实现与早期NAS（基于EA的RL的）方法相比提高效率的能力。最近的可分辨率NAS还旨在进一步提高搜索效率，降低GPU记忆消耗，并解决“深度间隙”问题。然而，这些方法不再能够解决非微弱目标，更不用说多目标，例如性能，鲁棒性，效率和其他指标。我们提出了一个端到端的架构搜索框架，朝向非微弱的目标TND-NAS，具有在多目标NAs（MNA）中的不同NAS框架中的高效率的优点和兼容性的兼容性（MNA）。在可分辨率的NAS框架下，随着搜索空间的连续放松，TND-NAS具有在离散空间中优化的架构参数（$ \ alpha $），同时通过$ \ alpha $逐步缩小超缩小的搜索策略。我们的代表性实验需要两个目标（参数，准确性），例如，我们在CIFAR10上实现了一系列高性能紧凑型架构（1.09米/ 3.3％，2.4M / 2.95％，9.57M / 2.54％）和CIFAR100（2.46 M / 18.3％，5.46 / 16.73％，12.88 / 15.20％）数据集。有利地，在现实世界的情景下（资源受限，平台专用），TND-NA可以方便地达到Pareto-Optimal解决方案。

我们日常生活中的深度学习是普遍存在的，包括自驾车，虚拟助理，社交网络服务，医疗服务，面部识别等，但是深度神经网络在训练和推理期间需要大量计算资源。该机器学习界主要集中在模型级优化（如深度学习模型的架构压缩），而系统社区则专注于实施级别优化。在其间，在算术界中提出了各种算术级优化技术。本文在模型，算术和实施级技术方面提供了关于资源有效的深度学习技术的调查，并确定了三种不同级别技术的资源有效的深度学习技术的研究差距。我们的调查基于我们的资源效率度量定义，阐明了较低级别技术的影响，并探讨了资源有效的深度学习研究的未来趋势。