深度学习（DL）改变了广泛行业的自动化，并发现社会上的普遍性日益增加。 DL模型及其广泛采用的高复杂性导致全球能源消耗每3-4个月增加一倍。当前，DL模型配置与能耗之间的关系尚未确定。在一般的计算能量模型级别上，硬件体系结构既有很强的依赖性（例如，具有不同配置的内部组件的通用处理器 - CPU和GPU，可编程的集成电路 - FPGA），以及不同的交互能量消耗方面（例如，。 ，数据运动，计算，控制）。在DL模型级别上，我们需要将非线性激活功能及其与数据的相互作用转换为计算任务。当前方法主要将非线性DL模型线性化，以近似其理论失败和MAC作为能源消耗的代理。然而，由于许多卷积神经网络（CNN）的高度非线性性质，这是不准确的（Est。93\％的精度）。在本文中，我们开发了一种底层晶体管操作（TOS）方法，以揭示非线性激活函数和神经网络结构在能量消耗中的作用。我们将一系列FeedForward和CNN模型转换为ALU计算任务，然后将其转换为步骤。然后，通过用于不同硬件配置和数据集的回归模型将其统计地链接到真实的能源消耗值。我们表明，我们提出的TOS方法可以在预测其能源消耗时获得93.61％-99.51％的精度。

我们日常生活中的深度学习是普遍存在的，包括自驾车，虚拟助理，社交网络服务，医疗服务，面部识别等，但是深度神经网络在训练和推理期间需要大量计算资源。该机器学习界主要集中在模型级优化（如深度学习模型的架构压缩），而系统社区则专注于实施级别优化。在其间，在算术界中提出了各种算术级优化技术。本文在模型，算术和实施级技术方面提供了关于资源有效的深度学习技术的调查，并确定了三种不同级别技术的资源有效的深度学习技术的研究差距。我们的调查基于我们的资源效率度量定义，阐明了较低级别技术的影响，并探讨了资源有效的深度学习研究的未来趋势。

Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems.This article aims to provide a comprehensive tutorial and survey about the recent advances towards the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic co-designs, being proposed in academia and industry.The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the trade-offs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

基于von-neumann架构的传统计算系统，数据密集型工作负载和应用程序（如机器学习）和应用程序都是基本上限制的。随着数据移动操作和能量消耗成为计算系统设计中的关键瓶颈，对近数据处理（NDP），机器学习和特别是神经网络（NN）的加速器等非传统方法的兴趣显着增加。诸如Reram和3D堆叠的新兴内存技术，这是有效地架构基于NN的基于NN的加速器，因为它们的工作能力是：高密度/低能量存储和近记忆计算/搜索引擎。在本文中，我们提出了一种为NN设计NDP架构的技术调查。通过基于所采用的内存技术对技术进行分类，我们强调了它们的相似之处和差异。最后，我们讨论了需要探索的开放挑战和未来的观点，以便改进和扩展未来计算平台的NDP架构。本文对计算机学习领域的计算机架构师，芯片设计师和研究人员来说是有价值的。

Resistive Random-Access Memory (RRAM) is well-suited to accelerate neural network (NN) workloads as RRAM-based Processing-in-Memory (PIM) architectures natively support highly-parallel multiply-accumulate (MAC) operations that form the backbone of most NN workloads. Unfortunately, NN workloads such as transformers require support for non-MAC operations (e.g., softmax) that RRAM cannot provide natively. Consequently, state-of-the-art works either integrate additional digital logic circuits to support the non-MAC operations or offload the non-MAC operations to CPU/GPU, resulting in significant performance and energy efficiency overheads due to data movement. In this work, we propose NEON, a novel compiler optimization to enable the end-to-end execution of the NN workload in RRAM. The key idea of NEON is to transform each non-MAC operation into a lightweight yet highly-accurate neural network. Utilizing neural networks to approximate the non-MAC operations provides two advantages: 1) We can exploit the key strength of RRAM, i.e., highly-parallel MAC operation, to flexibly and efficiently execute non-MAC operations in memory. 2) We can simplify RRAM's microarchitecture by eliminating the additional digital logic circuits while reducing the data movement overheads. Acceleration of the non-MAC operations in memory enables NEON to achieve a 2.28x speedup compared to an idealized digital logic-based RRAM. We analyze the trade-offs associated with the transformation and demonstrate feasible use cases for NEON across different substrates.

我们介绍了MLPERF小型推理基准（FPGA）平台上MLPERF微小的推理基准的最新结果。我们使用开源HLS4ML和Finn工作流，旨在使FPGA中优化神经网络的AI硬件代码民主化。我们介绍关键字发现，异常检测和图像分类基准任务的设计和实现过程。最终的硬件实现是针对速度和效率量身定制的，可配置的，可配置的空间数据流体系结构，并引入了新的通用优化和作为本工作的一部分开发的常见工作流程。完整的工作流程从量化感知培训到FPGA实施。该解决方案部署在芯片（PYNQ-Z2）和纯FPGA（ARTY A7-100T）平台上。由此产生的提交的潜伏期低至20 $ \ mu $ s和每次推论的低至30 $ \ mu $ j的能耗。我们展示了异质硬件平台上新兴的ML基准如何催化协作和开发新技术和更容易访问的工具。

When training early-stage deep neural networks (DNNs), generating intermediate features via convolution or linear layers occupied most of the execution time. Accordingly, extensive research has been done to reduce the computational burden of the convolution or linear layers. In recent mobile-friendly DNNs, however, the relative number of operations involved in processing these layers has significantly reduced. As a result, the proportion of the execution time of other layers, such as batch normalization layers, has increased. Thus, in this work, we conduct a detailed analysis of the batch normalization layer to efficiently reduce the runtime overhead in the batch normalization process. Backed up by the thorough analysis, we present an extremely efficient batch normalization, named LightNorm, and its associated hardware module. In more detail, we fuse three approximation techniques that are i) low bit-precision, ii) range batch normalization, and iii) block floating point. All these approximate techniques are carefully utilized not only to maintain the statistics of intermediate feature maps, but also to minimize the off-chip memory accesses. By using the proposed LightNorm hardware, we can achieve significant area and energy savings during the DNN training without hurting the training accuracy. This makes the proposed hardware a great candidate for the on-device training.

在本文中，我们提供了一种系统的方法来评估和比较数字信号处理中神经网络层的计算复杂性。我们提供并链接四个软件到硬件的复杂性度量，定义了不同的复杂度指标与层的超参数的关系。本文解释了如何计算这四个指标以进行馈送和经常性层，并定义在这种情况下，我们应该根据我们是否表征了面向更软件或硬件的应用程序来使用特定的度量。新引入的四个指标之一，称为“添加和位移位数（NAB）”，用于异质量化。 NABS不仅表征了操作中使用的位宽的影响，还表征了算术操作中使用的量化类型。我们打算这项工作作为与神经网络在实时数字信号处理中应用相关的复杂性估计级别（目的）的基线，旨在统一计算复杂性估计。

深神经网络（DNNS）在各种机器学习（ML）应用程序中取得了巨大成功，在计算机视觉，自然语言处理和虚拟现实等中提供了高质量的推理解决方案。但是，基于DNN的ML应用程序也带来计算和存储要求的增加了很多，对于具有有限的计算/存储资源，紧张的功率预算和较小形式的嵌入式系统而言，这尤其具有挑战性。挑战还来自各种特定应用的要求，包括实时响应，高通量性能和可靠的推理准确性。为了应对这些挑战，我们介绍了一系列有效的设计方法，包括有效的ML模型设计，定制的硬件加速器设计以及硬件/软件共同设计策略，以启用嵌入式系统上有效的ML应用程序。

在小型电池约束的物流设备上部署现代TinyML任务需要高计算能效。使用非易失性存储器（NVM）的模拟内存计算（IMC）承诺在深神经网络（DNN）推理中的主要效率提高，并用作DNN权重的片上存储器存储器。然而，在系统级别尚未完全理解IMC的功能灵活性限制及其对性能，能量和面积效率的影响。为了目标实际的端到端的IOT应用程序，IMC阵列必须括在异构可编程系统中，引入我们旨在解决这项工作的新系统级挑战。我们介绍了一个非均相紧密的聚类架构，整合了8个RISC-V核心，内存计算加速器（IMA）和数字加速器。我们在高度异构的工作负载上基准测试，例如来自MobileNetv2的瓶颈层，显示出11.5倍的性能和9.5倍的能效改进，而在核心上高度优化并行执行相比。此外，我们通过将我们的异构架构缩放到多阵列加速器，探讨了在IMC阵列资源方面对全移动级DNN（MobileNetv2）的端到端推断的要求。我们的结果表明，我们的解决方案在MobileNetv2的端到端推断上，在执行延迟方面比现有的可编程架构更好，比最先进的异构解决方案更好的数量级集成内存计算模拟核心。

深度神经网络（DNNS）的边缘训练是持续学习的理想目标。但是，这受到训练所需的巨大计算能力的阻碍。硬件近似乘数表明，它们在获得DNN推理加速器中获得资源效率的有效性；但是，使用近似乘数的培训在很大程度上尚未开发。为了通过支持DNN培训的近似乘数来构建有效的资源加速器，需要对不同DNN体系结构和不同近似乘数进行彻底评估。本文介绍了近似值，这是一个开源框架，允许使用模拟近似乘数快速评估DNN训练和推理。近似值与TensorFlow（TF）一样用户友好，仅需要对DNN体系结构的高级描述以及近似乘数的C/C ++功能模型。我们通过使用GPU（AMSIM）上的基于基于LUT的近似浮点（FP）乘数模拟器来提高乘数在乘数级别的模拟速度。近似值利用CUDA并有效地将AMSIM集成到张量库中，以克服商业GPU中的本机硬件近似乘数的缺乏。我们使用近似值来评估使用LENET和RESNETS体系结构的小型和大型数据集（包括Imagenet）的近似乘数的DNN训练的收敛性和准确性。与FP32和BFLOAT16乘数相比，评估表明测试准确性相似的收敛行为和可忽略不计的变化。与训练和推理中基于CPU的近似乘数模拟相比，GPU加速近似值快2500倍以上。基于具有本地硬件乘数的高度优化的闭合源Cudnn/Cublas库，原始张量量仅比近似值快8倍。

深入学习模型的压缩在将这些模型部署到边缘设备方面具有根本重要性。在压缩期间，在压缩期间结合硬件模型和应用限制可以最大限度地提高优势，但使其专为一种情况而设计。因此，压缩需要自动化。搜索最佳压缩方法参数被认为是一个优化问题。本文介绍了一种多目标硬件感知量化（MohaQ）方法，其将硬件效率和推理误差视为混合精度量化的目标。该方法通过依赖于两个步骤，在很大的搜索空间中评估候选解决方案。首先，应用训练后量化以进行快速解决方案评估。其次，我们提出了一个名为“基于信标的搜索”的搜索技术，仅在搜索空间中重新选出所选解决方案，并将其用作信标以了解刷新对其他解决方案的影响。为了评估优化潜力，我们使用Timit DataSet选择语音识别模型。该模型基于简单的复发单元（SRU），由于其相当大的加速在其他复发单元上。我们应用了我们在两个平台上运行的方法：SILAGO和BETFUSION。实验评估表明，SRU通过训练后量化可以压缩高达8倍，而误差的任何显着增加，误差只有1.5个百分点增加。在Silago上，唯一的搜索发现解决方案分别实现了最大可能加速和节能的80 \％和64 \％，错误的误差增加了0.5个百分点。在BETFUSION上，对于小SRAM尺寸的约束，基于信标的搜索将推断搜索的错误增益减少4个百分点，并且与BitFusion基线相比，可能的达到的加速度增加到47倍。

最新的努力改善了满足当今应用程序要求的神经网络（NN）加速器的性能，这引起了基于逻辑NN推理的新趋势，该趋势依赖于固定功能组合逻辑。将如此大的布尔函数与许多输入变量和产品项绘制到现场可编程门阵列（FPGA）上的数字信号处理器（DSP）需要一个新颖的框架，考虑到此过程中DSP块的结构和可重构性。本文中提出的方法将固定功能组合逻辑块映射到一组布尔功能，其中与每个功能相对应的布尔操作映射到DSP设备，而不是FPGA上的查找表（LUTS），以利用高性能，DSP块的低潜伏期和并行性。 ％本文还提出了一种用于NNS编译和映射的创新设计和优化方法，并利用固定功能组合逻辑与DSP进行了使用高级合成流的FPGA上的DSP。 ％我们在几个\ revone {DataSets}上进行的实验评估和选定的NNS与使用DSP的基于ART FPGA的NN加速器相比，根据推理潜伏期和输出准确性，证明了我们框架的可比性。

We introduce a method to train Quantized Neural Networks (QNNs) -neural networks with extremely low precision (e.g., 1-bit) weights and activations, at run-time. At traintime the quantized weights and activations are used for computing the parameter gradients. During the forward pass, QNNs drastically reduce memory size and accesses, and replace most arithmetic operations with bit-wise operations. As a result, power consumption is expected to be drastically reduced. We trained QNNs over the MNIST, CIFAR-10, SVHN and ImageNet datasets. The resulting QNNs achieve prediction accuracy comparable to their 32-bit counterparts. For example, our quantized version of AlexNet with 1-bit weights and 2-bit activations achieves 51% top-1 accuracy. Moreover, we quantize the parameter gradients to 6-bits as well which enables gradients computation using only bit-wise operation. Quantized recurrent neural networks were tested over the Penn Treebank dataset, and achieved comparable accuracy as their 32-bit counterparts using only 4-bits. Last but not least, we programmed a binary matrix multiplication GPU kernel with which it is possible to run our MNIST QNN 7 times faster than with an unoptimized GPU kernel, without suffering any loss in classification accuracy. The QNN code is available online.

With an ever-growing number of parameters defining increasingly complex networks, Deep Learning has led to several breakthroughs surpassing human performance. As a result, data movement for these millions of model parameters causes a growing imbalance known as the memory wall. Neuromorphic computing is an emerging paradigm that confronts this imbalance by performing computations directly in analog memories. On the software side, the sequential Backpropagation algorithm prevents efficient parallelization and thus fast convergence. A novel method, Direct Feedback Alignment, resolves inherent layer dependencies by directly passing the error from the output to each layer. At the intersection of hardware/software co-design, there is a demand for developing algorithms that are tolerable to hardware nonidealities. Therefore, this work explores the interrelationship of implementing bio-plausible learning in-situ on neuromorphic hardware, emphasizing energy, area, and latency constraints. Using the benchmarking framework DNN+NeuroSim, we investigate the impact of hardware nonidealities and quantization on algorithm performance, as well as how network topologies and algorithm-level design choices can scale latency, energy and area consumption of a chip. To the best of our knowledge, this work is the first to compare the impact of different learning algorithms on Compute-In-Memory-based hardware and vice versa. The best results achieved for accuracy remain Backpropagation-based, notably when facing hardware imperfections. Direct Feedback Alignment, on the other hand, allows for significant speedup due to parallelization, reducing training time by a factor approaching N for N-layered networks.

Spiking Neural Networks (SNNs) have gained huge attention as a potential energy-efficient alternative to conventional Artificial Neural Networks (ANNs) due to their inherent high-sparsity activation. Recently, SNNs with backpropagation through time (BPTT) have achieved a higher accuracy result on image recognition tasks than other SNN training algorithms. Despite the success from the algorithm perspective, prior works neglect the evaluation of the hardware energy overheads of BPTT due to the lack of a hardware evaluation platform for this SNN training algorithm. Moreover, although SNNs have long been seen as an energy-efficient counterpart of ANNs, a quantitative comparison between the training cost of SNNs and ANNs is missing. To address the aforementioned issues, in this work, we introduce SATA (Sparsity-Aware Training Accelerator), a BPTT-based training accelerator for SNNs. The proposed SATA provides a simple and re-configurable systolic-based accelerator architecture, which makes it easy to analyze the training energy for BPTT-based SNN training algorithms. By utilizing the sparsity, SATA increases its computation energy efficiency by $5.58 \times$ compared to the one without using sparsity. Based on SATA, we show quantitative analyses of the energy efficiency of SNN training and compare the training cost of SNNs and ANNs. The results show that, on Eyeriss-like systolic-based architecture, SNNs consume $1.27\times$ more total energy with sparsities when compared to ANNs. We find that such high training energy cost is from time-repetitive convolution operations and data movements during backpropagation. Moreover, to propel the future SNN training algorithm design, we provide several observations on energy efficiency for different SNN-specific training parameters and propose an energy estimation framework for SNN training. Code for our framework is made publicly available.

While machine learning is traditionally a resource intensive task, embedded systems, autonomous navigation, and the vision of the Internet of Things fuel the interest in resource-efficient approaches. These approaches aim for a carefully chosen trade-off between performance and resource consumption in terms of computation and energy. The development of such approaches is among the major challenges in current machine learning research and key to ensure a smooth transition of machine learning technology from a scientific environment with virtually unlimited computing resources into everyday's applications. In this article, we provide an overview of the current state of the art of machine learning techniques facilitating these real-world requirements. In particular, we focus on deep neural networks (DNNs), the predominant machine learning models of the past decade. We give a comprehensive overview of the vast literature that can be mainly split into three non-mutually exclusive categories: (i) quantized neural networks, (ii) network pruning, and (iii) structural efficiency. These techniques can be applied during training or as post-processing, and they are widely used to reduce the computational demands in terms of memory footprint, inference speed, and energy efficiency. We also briefly discuss different concepts of embedded hardware for DNNs and their compatibility with machine learning techniques as well as potential for energy and latency reduction. We substantiate our discussion with experiments on well-known benchmark datasets using compression techniques (quantization, pruning) for a set of resource-constrained embedded systems, such as CPUs, GPUs and FPGAs. The obtained results highlight the difficulty of finding good trade-offs between resource efficiency and predictive performance.

与变压器架构相关的自我监督学习的最新进展使自然语言处理（NLP）表现出极低的困惑。如此强大的模型需要越来越多的模型大小，因此需要大量的计算和内存足迹。在本文中，我们为大规模生成语言模型提出了一个有效的推理框架。作为减少模型大小的关键，我们通过不均匀的量化方法量化权重。然后，我们提出的称为NUQMM的量化矩阵乘法加速了，该内核可以在压缩比和准确性之间进行广泛的权衡。我们提出的NUQMM不仅减少了每个GPU的延迟，还减少了大LMS的全部推断，因为高压缩比（通过低位量化）减轻了最小所需的GPU数量。我们证明NUQMM可以将GPT-3（175b）模型的推理速度加速约14.4倍，并将能源消耗降低93％。

基于惯性数据的人类活动识别（HAR）是从智能手机到超低功率传感器的嵌入式设备上越来越扩散的任务。由于深度学习模型的计算复杂性很高，因此大多数嵌入式HAR系统基于简单且不那么精确的经典机器学习算法。这项工作弥合了在设备上的HAR和深度学习之间的差距，提出了一组有效的一维卷积神经网络（CNN），可在通用微控制器（MCUS）上部署。我们的CNN获得了将超参数优化与子字节和混合精确量化的结合，以在分类结果和记忆职业之间找到良好的权衡。此外，我们还利用自适应推断作为正交优化，以根据处理后的输入来调整运行时的推理复杂性，从而产生更灵活的HAR系统。通过在四个数据集上进行实验，并针对超低功率RISC-V MCU，我们表明（i）我们能够为HAR获得一组丰富的帕累托（Pareto）最佳CNN，以范围超过1个数量级记忆，潜伏期和能耗； （ii）由于自适应推断，我们可以从单个CNN开始得出> 20个运行时操作模式，分类分数的不同程度高达10％，并且推理复杂性超过3倍，并且内存开销有限； （iii）在四个基准中的三个基准中，我们的表现都超过了所有以前的深度学习方法，将记忆占用率降低了100倍以上。获得更好性能（浅层和深度）的少数方法与MCU部署不兼容。 （iv）我们所有的CNN都与推理延迟<16ms的实时式evice Har兼容。他们的记忆职业在0.05-23.17 kb中有所不同，其能源消耗为0.005和61.59 UJ，可在较小的电池供应中进行多年的连续操作。

已经证明量化是提高深神经网络推理效率的重要方法（DNN）。然而，在将DNN权重或从高精度格式从高精度格式量化到它们量化的对应物的同时，在准确性和效率之间取得良好的平衡仍然具有挑战性。我们提出了一种称为弹性显着位量化（ESB）的新方法，可控制量化值的有效位数，以获得具有更少资源的更好的推理准确性。我们设计一个统一的数学公式，以限制ESB的量化值，具有灵活的有效位。我们还引入了分布差对准器（DDA），以定量对齐全精密重量或激活值和量化值之间的分布。因此，ESB适用于各种重量和DNN的激活的各种钟形分布，从而保持高推理精度。从较少的量化值中受益于较少的量化值，ESB可以降低乘法复杂性。我们将ESB实施为加速器，并定量评估其对FPGA的效率。广泛的实验结果表明，ESB量化始终如一地优于最先进的方法，并分别通过AlexNet，Resnet18和MobileNetv2的平均精度提高4.78％，1.92％和3.56％。此外，ESB作为加速器可以在Xilinx ZCU102 FPGA平台上实现1K LUT的10.95 GOPS峰值性能。与FPGA上的CPU，GPU和最先进的加速器相比，ESB加速器可以分别将能效分别提高到65倍，11x和26倍。