在当今的数据密集型时代，深度学习非常普遍。特别是，卷积神经网络（CNN）在各种领域被广泛采用，以获得卓越的准确性。但是，计算传统CPU和GPU的深入CNN带来了几种性能和能量陷阱。最近已经证明了基于ASIC，FPGA和电阻内存设备的几种新型方法，并有令人鼓舞的结果。他们中的大多数仅针对深度学习的推理（测试）阶段。尝试设计能够培训和推理的全面深度学习加速器的尝试非常有限。这是由于训练阶段的高度计算和记忆密集型性质。在本文中，我们提出了一种新型的模拟光子CNN加速器Litecon。 Litecon使用基于硅微波炉的卷积，基于备忘录的内存和密集波长 - 划分的稳定和超快深度学习。我们使用商业CAD框架（IPKISS）评估LiteCon，该框架（IPKISS）在包括Lenet和VGG-NET在内的深度学习基准模型上评估。与最先进的情况相比，LiteCon分别将CNN的吞吐量，能源效率和计算效率提高了32倍，37倍和5倍，并具有微不足道的精度降解。

Deep neural networks (DNNs) are currently widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, techniques that enable efficient processing of DNNs to improve energy efficiency and throughput without sacrificing application accuracy or increasing hardware cost are critical to the wide deployment of DNNs in AI systems.This article aims to provide a comprehensive tutorial and survey about the recent advances towards the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNNs, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes. It will also summarize various development resources that enable researchers and practitioners to quickly get started in this field, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of DNN hardware designs, optionally including algorithmic co-designs, being proposed in academia and industry.The reader will take away the following concepts from this article: understand the key design considerations for DNNs; be able to evaluate different DNN hardware implementations with benchmarks and comparison metrics; understand the trade-offs between various hardware architectures and platforms; be able to evaluate the utility of various DNN design techniques for efficient processing; and understand recent implementation trends and opportunities.

基于von-neumann架构的传统计算系统，数据密集型工作负载和应用程序（如机器学习）和应用程序都是基本上限制的。随着数据移动操作和能量消耗成为计算系统设计中的关键瓶颈，对近数据处理（NDP），机器学习和特别是神经网络（NN）的加速器等非传统方法的兴趣显着增加。诸如Reram和3D堆叠的新兴内存技术，这是有效地架构基于NN的基于NN的加速器，因为它们的工作能力是：高密度/低能量存储和近记忆计算/搜索引擎。在本文中，我们提出了一种为NN设计NDP架构的技术调查。通过基于所采用的内存技术对技术进行分类，我们强调了它们的相似之处和差异。最后，我们讨论了需要探索的开放挑战和未来的观点，以便改进和扩展未来计算平台的NDP架构。本文对计算机学习领域的计算机架构师，芯片设计师和研究人员来说是有价值的。

近年来，人工智能（AI）的领域已经见证了巨大的增长，然而，持续发展的一些最紧迫的挑战是电子计算机架构所面临的基本带宽，能效和速度限制。利用用于执行神经网络推理操作的光子处理器越来越感兴趣，但是这些网络目前使用标准数字电子培训。这里，我们提出了由CMOS兼容的硅光子架构实现的神经网络的片上训练，以利用大规模平行，高效和快速数据操作的电位。我们的方案采用直接反馈对准训练算法，它使用错误反馈而不是错误反向化而培训神经网络，并且可以在每秒乘以数万亿乘以量的速度运行，同时每次MAC操作消耗小于一个微微约会。光子架构利用并行化矩阵 - 向量乘法利用微址谐振器阵列，用于沿着单个波导总线处理多通道模拟信号，以便原位计算每个神经网络层的梯度向量，这是在后向通过期间执行的最昂贵的操作。 。我们还通过片上MAC操作结果实验地示意使用MNIST数据集进行培训深度神经网络。我们的高效，超快速神经网络训练的新方法展示了光子学作为执行AI应用的有希望的平台。

稀疏卷积神经网络（CNNS）在过去几年中获得了显着的牵引力，因为与其致密的对应物相比，稀疏的CNNS可以大大降低模型尺寸和计算。稀疏的CNN经常引入层形状和尺寸的变化，这可以防止密集的加速器在稀疏的CNN模型上执行良好。最近提出的稀疏加速器，如SCNN，Eyeriss V2和Sparten，积极利用双面或全稀稀物质，即重量和激活的稀疏性，用于性能收益。然而，这些加速器具有低效的微架构，其限制了它们的性能，而不对非单位步幅卷积和完全连接（Fc）层的支持，或者遭受系统负荷不平衡的大规模遭受。为了规避这些问题并支持稀疏和密集的模型，我们提出了幻影，多线程，动态和灵活的神经计算核心。 Phantom使用稀疏二进制掩码表示，以主动寻求稀疏计算，并动态调度其计算线程以最大化线程利用率和吞吐量。我们还生成了幻象神经计算核心的二维（2D）网格体系结构，我们将其称为Phantom-2D加速器，并提出了一种支持CNN的所有层的新型数据流，包括单位和非单位步幅卷积，和fc层。此外，Phantom-2D使用双级负载平衡策略来最小化计算空闲，从而进一步提高硬件利用率。为了向不同类型的图层显示支持，我们评估VGG16和MobileNet上的幻影架构的性能。我们的模拟表明，Phantom-2D加速器分别达到了12倍，4.1 X，1.98x和2.36倍，超密架构，SCNN，Sparten和Eyeriss V2的性能增益。

The last few years have seen a lot of work to address the challenge of low-latency and high-throughput convolutional neural network inference. Integrated photonics has the potential to dramatically accelerate neural networks because of its low-latency nature. Combined with the concept of Joint Transform Correlator (JTC), the computationally expensive convolution functions can be computed instantaneously (time of flight of light) with almost no cost. This 'free' convolution computation provides the theoretical basis of the proposed PhotoFourier JTC-based CNN accelerator. PhotoFourier addresses a myriad of challenges posed by on-chip photonic computing in the Fourier domain including 1D lenses and high-cost optoelectronic conversions. The proposed PhotoFourier accelerator achieves more than 28X better energy-delay product compared to state-of-art photonic neural network accelerators.

由于深度学习在许多人工智能应用中显示了革命性的性能，其升级的计算需求需要用于巨大并行性的硬件加速器和改进的吞吐量。光学神经网络（ONN）是下一代神经关键组成的有希望的候选者，由于其高并行，低延迟和低能量消耗。在这里，我们设计了一个硬件高效的光子子空间神经网络（PSNN）架构，其针对具有比具有可比任务性能的前一个ONN架构的光学元件使用，区域成本和能量消耗。此外，提供了一种硬件感知培训框架，以最小化所需的设备编程精度，减少芯片区域，并提高噪声鲁棒性。我们在实验上展示了我们的PSNN在蝴蝶式可编程硅光子集成电路上，并在实用的图像识别任务中显示其实用性。

我们日常生活中的深度学习是普遍存在的，包括自驾车，虚拟助理，社交网络服务，医疗服务，面部识别等，但是深度神经网络在训练和推理期间需要大量计算资源。该机器学习界主要集中在模型级优化（如深度学习模型的架构压缩），而系统社区则专注于实施级别优化。在其间，在算术界中提出了各种算术级优化技术。本文在模型，算术和实施级技术方面提供了关于资源有效的深度学习技术的调查，并确定了三种不同级别技术的资源有效的深度学习技术的研究差距。我们的调查基于我们的资源效率度量定义，阐明了较低级别技术的影响，并探讨了资源有效的深度学习研究的未来趋势。

在本文中，提出了一种新的方法，该方法允许基于神经网络（NN）均衡器的低复杂性发展，以缓解高速相干光学传输系统中的损伤。在这项工作中，我们提供了已应用于馈电和经常性NN设计的各种深层模型压缩方法的全面描述和比较。此外，我们评估了这些策略对每个NN均衡器的性能的影响。考虑量化，重量聚类，修剪和其他用于模型压缩的尖端策略。在这项工作中，我们提出并评估贝叶斯优化辅助压缩，其中选择了压缩的超参数以同时降低复杂性并提高性能。总之，通过使用模拟和实验数据来评估每种压缩方法的复杂性及其性能之间的权衡，以完成分析。通过利用最佳压缩方法，我们表明可以设计基于NN的均衡器，该均衡器比传统的数字背部传播（DBP）均衡器具有更好的性能，并且只有一个步骤。这是通过减少使用加权聚类和修剪算法后在NN均衡器中使用的乘数数量来完成的。此外，我们证明了基于NN的均衡器也可以实现卓越的性能，同时仍然保持与完整的电子色色散补偿块相同的复杂性。我们通过强调开放问题和现有挑战以及未来的研究方向来结束分析。

具有最小延迟的人工神经网络的决策对于诸如导航，跟踪和实时机器动作系统之类的许多应用来说是至关重要的。这要求机器学习硬件以高吞吐量处理多维数据。不幸的是，处理卷积操作是数据分类任务的主要计算工具，遵循有挑战性的运行时间复杂性缩放法。然而，在傅立叶光学显示器 - 光处理器中同心地实现卷积定理，使得不迭代的O（1）运行时复杂度以超过1,000×1,000大矩阵的数据输入。在此方法之后，这里我们展示了具有傅里叶卷积神经网络（FCNN）加速器的数据流多核图像批处理。我们将大规模矩阵的图像批量处理显示为傅立叶域中的数字光处理模块执行的被动的2000万点产品乘法。另外，我们通过利用多种时空衍射令并进一步并行化该光学FCNN系统，从而实现了最先进的FCNN加速器的98倍的产量改进。综合讨论与系统能力边缘工作相关的实际挑战突出了傅立叶域和决议缩放法律的串扰问题。通过利用展示技术中的大规模平行性加速卷积带来了基于VAN Neuman的机器学习加速度。

在小型电池约束的物流设备上部署现代TinyML任务需要高计算能效。使用非易失性存储器（NVM）的模拟内存计算（IMC）承诺在深神经网络（DNN）推理中的主要效率提高，并用作DNN权重的片上存储器存储器。然而，在系统级别尚未完全理解IMC的功能灵活性限制及其对性能，能量和面积效率的影响。为了目标实际的端到端的IOT应用程序，IMC阵列必须括在异构可编程系统中，引入我们旨在解决这项工作的新系统级挑战。我们介绍了一个非均相紧密的聚类架构，整合了8个RISC-V核心，内存计算加速器（IMA）和数字加速器。我们在高度异构的工作负载上基准测试，例如来自MobileNetv2的瓶颈层，显示出11.5倍的性能和9.5倍的能效改进，而在核心上高度优化并行执行相比。此外，我们通过将我们的异构架构缩放到多阵列加速器，探讨了在IMC阵列资源方面对全移动级DNN（MobileNetv2）的端到端推断的要求。我们的结果表明，我们的解决方案在MobileNetv2的端到端推断上，在执行延迟方面比现有的可编程架构更好，比最先进的异构解决方案更好的数量级集成内存计算模拟核心。

The ever-growing deep learning technologies are making revolutionary changes for modern life. However, conventional computing architectures are designed to process sequential and digital programs, being extremely burdened with performing massive parallel and adaptive deep learning applications. Photonic integrated circuits provide an efficient approach to mitigate bandwidth limitations and power-wall brought by its electronic counterparts, showing great potential in ultrafast and energy-free high-performance computing. Here, we propose an optical computing architecture enabled by on-chip diffraction to implement convolutional acceleration, termed optical convolution unit (OCU). We demonstrate that any real-valued convolution kernels can be exploited by OCU with a prominent computational throughput boosting via the concept of structral re-parameterization. With OCU as the fundamental unit, we build an optical convolutional neural network (oCNN) to implement two popular deep learning tasks: classification and regression. For classification, Fashion-MNIST and CIFAR-4 datasets are tested with accuracy of 91.63% and 86.25%, respectively. For regression, we build an optical denoising convolutional neural network (oDnCNN) to handle Gaussian noise in gray scale images with noise level {\sigma} = 10, 15, 20, resulting clean images with average PSNR of 31.70dB, 29.39dB and 27.72dB, respectively. The proposed OCU presents remarkable performance of low energy consumption and high information density due to its fully passive nature and compact footprint, providing a highly parallel while lightweight solution for future computing architecture to handle high dimensional tensors in deep learning.

配备高速数字化器的前端电子设备正在使用并建议将来的核检测器。最近的文献表明，在处理来自核检测器的数字信号时，深度学习模型，尤其是一维卷积神经网络。模拟和实验证明了该领域神经网络的令人满意的准确性和其他好处。但是，仍需要研究特定的硬件加速在线操作。在这项工作中，我们介绍了Pulsedl-II，这是一种专门设计的，专门为事件功能（时间，能量等）从具有深度学习的脉冲中提取的应用。根据先前的版本，PULSEDL-II将RISC CPU纳入系统结构，以更好地功能灵活性和完整性。 SOC中的神经网络加速器采用三级（算术单元，处理元件，神经网络）层次结构，并促进数字设计的参数优化。此外，我们设计了一种量化方案和相关的实现方法（恢复和位移位），以在所选层类型的选定子集中与深度学习框架（例如Tensorflow）完全兼容。通过当前方案，支持神经网络的量化训练，并通过专用脚本自动将网络模型转换为RISC CPU软件，几乎没有准确性损失。我们在现场可编程门阵列（FPGA）上验证pulsedl-ii。最后，通过由直接数字合成（DDS）信号发生器和带有模数转换器（ADC）的FPGA开发板组成的实验设置进行系统验证。拟议的系统实现了60 PS的时间分辨率和0.40％的能量分辨率，在线神经网络推断在信号与噪声比（SNR）为47.4 dB时。

While machine learning is traditionally a resource intensive task, embedded systems, autonomous navigation, and the vision of the Internet of Things fuel the interest in resource-efficient approaches. These approaches aim for a carefully chosen trade-off between performance and resource consumption in terms of computation and energy. The development of such approaches is among the major challenges in current machine learning research and key to ensure a smooth transition of machine learning technology from a scientific environment with virtually unlimited computing resources into everyday's applications. In this article, we provide an overview of the current state of the art of machine learning techniques facilitating these real-world requirements. In particular, we focus on deep neural networks (DNNs), the predominant machine learning models of the past decade. We give a comprehensive overview of the vast literature that can be mainly split into three non-mutually exclusive categories: (i) quantized neural networks, (ii) network pruning, and (iii) structural efficiency. These techniques can be applied during training or as post-processing, and they are widely used to reduce the computational demands in terms of memory footprint, inference speed, and energy efficiency. We also briefly discuss different concepts of embedded hardware for DNNs and their compatibility with machine learning techniques as well as potential for energy and latency reduction. We substantiate our discussion with experiments on well-known benchmark datasets using compression techniques (quantization, pruning) for a set of resource-constrained embedded systems, such as CPUs, GPUs and FPGAs. The obtained results highlight the difficulty of finding good trade-offs between resource efficiency and predictive performance.

当今的大多数计算机视觉管道都是围绕深神经网络构建的，卷积操作需要大部分一般的计算工作。与标准算法相比，Winograd卷积算法以更少的MAC计算卷积，当使用具有2x2尺寸瓷砖$ F_2 $的版本时，3x3卷积的操作计数为2.25倍。即使收益很大，Winograd算法具有较大的瓷砖尺寸，即$ f_4 $，在提高吞吐量和能源效率方面具有更大的潜力，因为它将所需的MAC降低了4倍。不幸的是，具有较大瓷砖尺寸的Winograd算法引入了数值问题，这些问题阻止了其在整数域特异性加速器上的使用和更高的计算开销，以在空间和Winograd域之间转换输入和输出数据。为了解锁Winograd $ F_4 $的全部潜力，我们提出了一种新颖的Tap-Wise量化方法，该方法克服了使用较大瓷砖的数值问题，从而实现了仅整数的推断。此外，我们介绍了以功率和区域效率的方式处理Winograd转换的自定义硬件单元，并展示了如何将此类自定义模块集成到工业级，可编程的DSA中。对大量最先进的计算机视觉基准进行了广泛的实验评估表明，Tap-Wise量化算法使量化的Winograd $ F_4 $网络几乎与FP32基线一样准确。 Winograd增强的DSA可实现高达1.85倍的能源效率，最高可用于最先进的细分和检测网络的端到端速度高达1.83倍。

With an ever-growing number of parameters defining increasingly complex networks, Deep Learning has led to several breakthroughs surpassing human performance. As a result, data movement for these millions of model parameters causes a growing imbalance known as the memory wall. Neuromorphic computing is an emerging paradigm that confronts this imbalance by performing computations directly in analog memories. On the software side, the sequential Backpropagation algorithm prevents efficient parallelization and thus fast convergence. A novel method, Direct Feedback Alignment, resolves inherent layer dependencies by directly passing the error from the output to each layer. At the intersection of hardware/software co-design, there is a demand for developing algorithms that are tolerable to hardware nonidealities. Therefore, this work explores the interrelationship of implementing bio-plausible learning in-situ on neuromorphic hardware, emphasizing energy, area, and latency constraints. Using the benchmarking framework DNN+NeuroSim, we investigate the impact of hardware nonidealities and quantization on algorithm performance, as well as how network topologies and algorithm-level design choices can scale latency, energy and area consumption of a chip. To the best of our knowledge, this work is the first to compare the impact of different learning algorithms on Compute-In-Memory-based hardware and vice versa. The best results achieved for accuracy remain Backpropagation-based, notably when facing hardware imperfections. Direct Feedback Alignment, on the other hand, allows for significant speedup due to parallelization, reducing training time by a factor approaching N for N-layered networks.

State-of-the-art deep neural networks (DNNs) have hundreds of millions of connections and are both computationally and memory intensive, making them difficult to deploy on embedded systems with limited hardware resources and power budgets. While custom hardware helps the computation, fetching weights from DRAM is two orders of magnitude more expensive than ALU operations, and dominates the required power.Previously proposed 'Deep Compression' makes it possible to fit large DNNs (AlexNet and VGGNet) fully in on-chip SRAM. This compression is achieved by pruning the redundant connections and having multiple connections share the same weight. We propose an energy efficient inference engine (EIE) that performs inference on this compressed network model and accelerates the resulting sparse matrix-vector multiplication with weight sharing. Going from DRAM to SRAM gives EIE 120× energy saving; Exploiting sparsity saves 10×; Weight sharing gives 8×; Skipping zero activations from ReLU saves another 3×. Evaluated on nine DNN benchmarks, EIE is 189× and 13× faster when compared to CPU and GPU implementations of the same DNN without compression. EIE has a processing power of 102 GOPS/s working directly on a compressed network, corresponding to 3 TOPS/s on an uncompressed network, and processes FC layers of AlexNet at 1.88×10 4 frames/sec with a power dissipation of only 600mW. It is 24,000× and 3,400× more energy efficient than a CPU and GPU respectively. Compared with DaDianNao, EIE has 2.9×, 19× and 3× better throughput, energy efficiency and area efficiency.

IOT应用中的总是关于Tinyml的感知任务需要非常高的能量效率。模拟计算内存（CIM）使用非易失性存储器（NVM）承诺高效率，并提供自包含的片上模型存储。然而，模拟CIM推出了新的实际考虑因素，包括电导漂移，读/写噪声，固定的模数转换器增益等。必须解决这些附加约束，以实现可以通过可接受的模拟CIM部署的模型精度损失。这项工作描述了$ \ textit {analognets} $：tinyml模型用于关键字点（kws）和视觉唤醒词（VWW）的流行始终是on。模型架构专门为模拟CIM设计，我们详细介绍了一种全面的培训方法，以在推理时间内保持面对模拟非理想的精度和低精度数据转换器。我们还描述了AON-CIM，可编程，最小面积的相变存储器（PCM）模拟CIM加速器，具有新颖的层串行方法，以消除与完全流水线设计相关的复杂互连的成本。我们在校准的模拟器以及真正的硬件中评估了对校准模拟器的矛盾，并发现精度下降限制为KWS / VWW的PCM漂移（8位）24小时后的0.8 $ \％$ / 1.2 $ \％$。在14nm AON-CIM加速器上运行的analognets使用8位激活，分别使用8位激活，并增加到57.39 / 25.69个顶部/ w，以4美元$ 4 $ 57.39 / 25.69。

随着深度神经网络（DNN）的发展以解决日益复杂的问题，它们正受到现有数字处理器的延迟和功耗的限制。为了提高速度和能源效率，已经提出了专门的模拟光学和电子硬件，但是可扩展性有限（输入矢量长度$ k $的数百个元素）。在这里，我们提出了一个可扩展的，单层模拟光学处理器，该光学处理器使用自由空间光学器件可重新配置输入向量和集成的光电，用于静态，可更新的加权和非线性 - 具有$ k \ \ 1,000 $和大约1,000美元和超过。我们通过实验测试MNIST手写数字数据集的分类精度，在没有数据预处理或在硬件上进行数据重新处理的情况下达到94.7％（地面真相96.3％）。我们还确定吞吐量（$ \ sim $ 0.9 examac/s）的基本上限，由最大光带宽设置，然后大大增加误差。我们在兼容CMOS兼容系统中宽光谱和空间带宽的组合可以实现下一代DNN的高效计算。

We introduce a method to train Quantized Neural Networks (QNNs) -neural networks with extremely low precision (e.g., 1-bit) weights and activations, at run-time. At traintime the quantized weights and activations are used for computing the parameter gradients. During the forward pass, QNNs drastically reduce memory size and accesses, and replace most arithmetic operations with bit-wise operations. As a result, power consumption is expected to be drastically reduced. We trained QNNs over the MNIST, CIFAR-10, SVHN and ImageNet datasets. The resulting QNNs achieve prediction accuracy comparable to their 32-bit counterparts. For example, our quantized version of AlexNet with 1-bit weights and 2-bit activations achieves 51% top-1 accuracy. Moreover, we quantize the parameter gradients to 6-bits as well which enables gradients computation using only bit-wise operation. Quantized recurrent neural networks were tested over the Penn Treebank dataset, and achieved comparable accuracy as their 32-bit counterparts using only 4-bits. Last but not least, we programmed a binary matrix multiplication GPU kernel with which it is possible to run our MNIST QNN 7 times faster than with an unoptimized GPU kernel, without suffering any loss in classification accuracy. The QNN code is available online.