神经形态计算机通过模拟人脑进行计算，并使用极低的功率。预计将来对于节能计算是必不可少的。尽管它们主要用于尖峰基于神经网络的机器学习应用程序，但已知神经形态计算机是Turing-Complete，因此能够进行通用计算。但是，为了充分意识到它们的通用，节能计算的潜力，重要的是要设计有效的编码数字机制。当前的编码方法的适用性有限，可能不适合通用计算。在本文中，我们将虚拟神经元视为整数和理性数字的编码机制。我们评估虚拟神经元在物理和模拟神经形态硬件上的性能，并表明它可以使用基于混合信号的Memristor神经形态处理器平均使用23 nj的能量执行加法操作。我们还通过在某些MU回复功能中使用它来证明其实用性，这些功能是通用计算的构建块。

神经形态工程由于其作为研究领域的巨大潜力而​​集中了大量研究人员的努力，以寻找对生物神经系统的优势的利用，而整个大脑的优势是设计更有效，更真实的 - 有能力的应用程序。为了开发尽可能接近生物学的应用，使用了尖峰神经网络（SNN），被认为是生物学上的，并构成了第三代人工神经网络（ANN）。由于某些基于SNN的应用程序可能需要存储数据才能以后使用，因此在数字电路中既存在，又以某种形式，在生物学中，需要尖峰内存。这项工作介绍了内存的尖峰实现，这是计算机架构中最重要的组件之一，在设计完全尖峰计算机时可能至关重要。在设计这种尖峰内存的过程中，还实施了不同的中间组件和测试。测试是在大三角帆神经形态平台上进行的，并允许验证用于构建所构图的方法。此外，这项工作深入研究了如何使用这种方法构建尖峰块，并包括IT和其他类似作品中使用的方法的比较，该作品着重于尖峰组件的设计，其中包括尖峰逻辑门和尖峰记忆。所有实施的块和开发的测试均可在公共存储库中提供。

The term ``neuromorphic'' refers to systems that are closely resembling the architecture and/or the dynamics of biological neural networks. Typical examples are novel computer chips designed to mimic the architecture of a biological brain, or sensors that get inspiration from, e.g., the visual or olfactory systems in insects and mammals to acquire information about the environment. This approach is not without ambition as it promises to enable engineered devices able to reproduce the level of performance observed in biological organisms -- the main immediate advantage being the efficient use of scarce resources, which translates into low power requirements. The emphasis on low power and energy efficiency of neuromorphic devices is a perfect match for space applications. Spacecraft -- especially miniaturized ones -- have strict energy constraints as they need to operate in an environment which is scarce with resources and extremely hostile. In this work we present an overview of early attempts made to study a neuromorphic approach in a space context at the European Space Agency's (ESA) Advanced Concepts Team (ACT).

尖峰神经网络（SNN）提供了一个新的计算范式，能够高度平行，实时处理。光子设备是设计与SNN计算范式相匹配的高带宽，平行体系结构的理想选择。 CMO和光子元件的协整允许将低损耗的光子设备与模拟电子设备结合使用，以更大的非线性计算元件的灵活性。因此，我们在整体硅光子学（SIPH）过程上设计和模拟了光电尖峰神经元电路，该过程复制了超出泄漏的集成和火（LIF）之外有用的尖峰行为。此外，我们探索了两种学习算法，具有使用Mach-Zehnder干涉法（MZI）网格作为突触互连的片上学习的潜力。实验证明了随机反向传播（RPB）的变体，并在简单分类任务上与标准线性回归的性能相匹配。同时，将对比性HEBBIAN学习（CHL）规则应用于由MZI网格组成的模拟神经网络，以进行随机输入输出映射任务。受CHL训练的MZI网络的性能比随机猜测更好，但不符合理想神经网络的性能（没有MZI网格施加的约束）。通过这些努力，我们证明了协调的CMO和SIPH技术非常适合可扩展的SNN计算体系结构的设计。

穗状花序的神经形状硬件占据了深度神经网络（DNN）的更节能实现的承诺，而不是GPU的标准硬件。但这需要了解如何在基于事件的稀疏触发制度中仿真DNN，否则能量优势丢失。特别地，解决序列处理任务的DNN通常采用难以使用少量尖峰效仿的长短期存储器（LSTM）单元。我们展示了许多生物神经元的面部，在每个尖峰后缓慢的超积极性（AHP）电流，提供了有效的解决方案。 AHP电流可以轻松地在支持多舱神经元模型的神经形状硬件中实现，例如英特尔的Loihi芯片。滤波近似理论解释为什么AHP-Neurons可以模拟LSTM单元的功能。这产生了高度节能的时间序列分类方法。此外，它为实现了非常稀疏的大量大型DNN来实现基础，这些大型DNN在文本中提取单词和句子之间的关系，以便回答有关文本的问题。

我们提出了Memprop，即采用基于梯度的学习来培训完全的申请尖峰神经网络（MSNNS）。我们的方法利用固有的设备动力学来触发自然产生的电压尖峰。这些由回忆动力学发出的尖峰本质上是类似物，因此完全可区分，这消除了尖峰神经网络（SNN）文献中普遍存在的替代梯度方法的需求。回忆性神经网络通常将备忘录集成为映射离线培训网络的突触，或者以其他方式依靠关联学习机制来训练候选神经元的网络。相反，我们直接在循环神经元和突触的模拟香料模型上应用了通过时间（BPTT）训练算法的反向传播。我们的实现是完全的综合性，因为突触重量和尖峰神经元都集成在电阻RAM（RRAM）阵列上，而无需其他电路来实现尖峰动态，例如模数转换器（ADCS）或阈值比较器。结果，高阶电物理效应被充分利用，以在运行时使用磁性神经元的状态驱动动力学。通过朝着非同一梯度的学习迈进，我们在以前报道的几个基准上的轻巧密集的完全MSNN中获得了高度竞争的准确性。

Spiking neural networks (SNN) are a viable alternative to conventional artificial neural networks when energy efficiency and computational complexity are of importance. A major advantage of SNNs is their binary information transfer through spike trains. The training of SNN has, however, been a challenge, since neuron models are non-differentiable and traditional gradient-based backpropagation algorithms cannot be applied directly. Furthermore, spike-timing-dependent plasticity (STDP), albeit being a spike-based learning rule, updates weights locally and does not optimize for the output error of the network. We present desire backpropagation, a method to derive the desired spike activity of neurons from the output error. The loss function can then be evaluated locally for every neuron. Incorporating the desire values into the STDP weight update leads to global error minimization and increasing classification accuracy. At the same time, the neuron dynamics and computational efficiency of STDP are maintained, making it a spike-based supervised learning rule. We trained three-layer networks to classify MNIST and Fashion-MNIST images and reached an accuracy of 98.41% and 87.56%, respectively. Furthermore, we show that desire backpropagation is computationally less complex than backpropagation in traditional neural networks.

Spiking Neural Networks (SNNs) are bio-plausible models that hold great potential for realizing energy-efficient implementations of sequential tasks on resource-constrained edge devices. However, commercial edge platforms based on standard GPUs are not optimized to deploy SNNs, resulting in high energy and latency. While analog In-Memory Computing (IMC) platforms can serve as energy-efficient inference engines, they are accursed by the immense energy, latency, and area requirements of high-precision ADCs (HP-ADC), overshadowing the benefits of in-memory computations. We propose a hardware/software co-design methodology to deploy SNNs into an ADC-Less IMC architecture using sense-amplifiers as 1-bit ADCs replacing conventional HP-ADCs and alleviating the above issues. Our proposed framework incurs minimal accuracy degradation by performing hardware-aware training and is able to scale beyond simple image classification tasks to more complex sequential regression tasks. Experiments on complex tasks of optical flow estimation and gesture recognition show that progressively increasing the hardware awareness during SNN training allows the model to adapt and learn the errors due to the non-idealities associated with ADC-Less IMC. Also, the proposed ADC-Less IMC offers significant energy and latency improvements, $2-7\times$ and $8.9-24.6\times$, respectively, depending on the SNN model and the workload, compared to HP-ADC IMC.

编译器框架对于广泛使用基于FPGA的深度学习加速器来说是至关重要的。它们允许研究人员和开发人员不熟悉硬件工程，以利用域特定逻辑所获得的性能。存在传统人工神经网络的各种框架。然而，没有多大的研究努力已经进入创建针对尖刺神经网络（SNNS）进行优化的框架。这种新一代的神经网络对于在边缘设备上部署AI的越来越有趣，其具有紧密的功率和资源约束。我们的端到端框架E3NE为FPGA自动生成高效的SNN推理逻辑。基于Pytorch模型和用户参数，它应用各种优化，并评估基于峰值的加速器固有的权衡。多个水平的并行性和新出现的神经编码方案的使用导致优于先前的SNN硬件实现的效率。对于类似的型号，E3NE使用的硬件资源的少于50％，功率较低20％，同时通过幅度降低延迟。此外，可扩展性和通用性允许部署大规模的SNN模型AlexNet和VGG。

更具体地说，神经系统能够简单有效地解决复杂的问题，超过现代计算机。在这方面，神经形态工程是一个研究领域，重点是模仿控制大脑的基本原理，以开发实现此类计算能力的系统。在该领域中，生物启发的学习和记忆系统仍然是要解决的挑战，这就是海马涉及的地方。正是大脑的区域充当短期记忆，从而从大脑皮层的所有感觉核中学习，非结构化和快速存储信息及其随后的回忆。在这项工作中，我们提出了一个基于海马的新型生物启发的记忆模型，具有学习记忆的能力，从提示中回顾它们（与其他内容相关的记忆的一部分），甚至在尝试时忘记记忆通过相同的提示学习其他人。该模型已在使用尖峰神经网络上在大型摩托车硬件平台上实现，并进行了一组实验和测试以证明其正确且预期的操作。所提出的基于SPIKE的内存模型仅在接收输入，能提供节能的情况下才能生成SPIKES，并且需要7个时间步，用于学习步骤和6个时间段来召回以前存储的存储器。这项工作介绍了基于生物启发的峰值海马记忆模型的第一个硬件实现，为开发未来更复杂的神经形态系统的发展铺平了道路。

Loihi is a 60-mm 2 chip fabricated in Intel's 14-nm process that advances the state-of-the-art modeling of spiking neural networks in silicon. It integrates a wide range of novel features for the field, such as hierarchical connectivity, dendritic compartments, synaptic delays, and, most importantly, programmable synaptic learning rules. Running a spiking convolutional form of the Locally Competitive Algorithm, Loihi can solve LASSO optimization problems with over three orders of magnitude superior energy-delay product compared to conventional solvers running on a CPU isoprocess/voltage/area. This provides an unambiguous example of spike-based computation, outperforming all known conventional solutions.Neuroscience offers a bountiful source of inspiration for novel hardware architectures and algorithms. Through their complex interactions at large scales, biological neurons exhibit an impressive range of behaviors and properties that we currently struggle to model with modern analytical tools, let alone replicate with our design and manufacturing technology. Some of the magic that we see in the brain undoubtedly stems from exotic device and material properties that will remain out of our fabs' reach for

In the past years, artificial neural networks (ANNs) have become the de-facto standard to solve tasks in communications engineering that are difficult to solve with traditional methods. In parallel, the artificial intelligence community drives its research to biology-inspired, brain-like spiking neural networks (SNNs), which promise extremely energy-efficient computing. In this paper, we investigate the use of SNNs in the context of channel equalization for ultra-low complexity receivers. We propose an SNN-based equalizer with a feedback structure akin to the decision feedback equalizer (DFE). For conversion of real-world data into spike signals we introduce a novel ternary encoding and compare it with traditional log-scale encoding. We show that our approach clearly outperforms conventional linear equalizers for three different exemplary channels. We highlight that mainly the conversion of the channel output to spikes introduces a small performance penalty. The proposed SNN with a decision feedback structure enables the path to competitive energy-efficient transceivers.

这项研究提出了依赖电压突触可塑性（VDSP），这是一种新型的脑启发的无监督的本地学习规则，用于在线实施HEBB对神经形态硬件的可塑性机制。拟议的VDSP学习规则仅更新了突触后神经元的尖峰的突触电导，这使得相对于标准峰值依赖性可塑性（STDP）的更新数量减少了两倍。此更新取决于突触前神经元的膜电位，该神经元很容易作为神经元实现的一部分，因此不需要额外的存储器来存储。此外，该更新还对突触重量进行了正规化，并防止重复刺激时的重量爆炸或消失。进行严格的数学分析以在VDSP和STDP之间达到等效性。为了验证VDSP的系统级性能，我们训练一个单层尖峰神经网络（SNN），以识别手写数字。我们报告85.01 $ \ pm $ 0.76％（平均$ \ pm $ s.d。）对于MNIST数据集中的100个输出神经元网络的精度。在缩放网络大小时，性能会提高（400个输出神经元的89.93 $ \ pm $ 0.41％，500个神经元为90.56 $ \ pm $ 0.27），这验证了大规模计算机视觉任务的拟议学习规则的适用性。有趣的是，学习规则比STDP更好地适应输入信号的频率，并且不需要对超参数进行手动调整。

Understanding how biological neural networks carry out learning using spike-based local plasticity mechanisms can lead to the development of powerful, energy-efficient, and adaptive neuromorphic processing systems. A large number of spike-based learning models have recently been proposed following different approaches. However, it is difficult to assess if and how they could be mapped onto neuromorphic hardware, and to compare their features and ease of implementation. To this end, in this survey, we provide a comprehensive overview of representative brain-inspired synaptic plasticity models and mixed-signal CMOS neuromorphic circuits within a unified framework. We review historical, bottom-up, and top-down approaches to modeling synaptic plasticity, and we identify computational primitives that can support low-latency and low-power hardware implementations of spike-based learning rules. We provide a common definition of a locality principle based on pre- and post-synaptic neuron information, which we propose as a fundamental requirement for physical implementations of synaptic plasticity. Based on this principle, we compare the properties of these models within the same framework, and describe the mixed-signal electronic circuits that implement their computing primitives, pointing out how these building blocks enable efficient on-chip and online learning in neuromorphic processing systems.

在过去的几十年中，人工智能领域大大进展，灵感来自生物学和神经科学领域的发现。这项工作的想法是由来自传入和横向/内部联系的人脑中皮质区域的自组织过程的过程启发。在这项工作中，我们开发了一个原始的脑激发神经模型，将自组织地图（SOM）和Hebbian学习在重新参与索马里（RESOM）模型中。该框架应用于多模式分类问题。与基于未经监督的学习的现有方法相比，该模型增强了最先进的结果。这项工作还通过在名为SPARP（自配置3D蜂窝自适应平台）的专用FPGA的平台上的模拟结果和硬件执行，演示了模型的分布式和可扩展性。头皮板可以以模块化方式互连，以支持神经模型的结构。这种统一的软件和硬件方法使得能够缩放处理并允许来自多个模态的信息进行动态合并。硬件板上的部署提供了在多个设备上并行执行的性能结果，通过专用串行链路在每个板之间的通信。由于多模式关联，所提出的统一架构，由RESOM模型和头皮硬件平台组成的精度显着提高，与集中式GPU实现相比，延迟和功耗之间的良好折衷。

神经形态计算是一个新兴的研究领域，旨在通过整合来自神经科学和深度学习等多学科的理论和技术来开发新的智能系统。当前，已经为相关字段开发了各种软件框架，但是缺乏专门用于基于Spike的计算模型和算法的有效框架。在这项工作中，我们提出了一个基于Python的尖峰神经网络（SNN）模拟和培训框架，又名Spaic，旨在支持脑启发的模型和算法研究，并与深度学习和神经科学的特征集成在一起。为了整合两个压倒性学科的不同方法，以及灵活性和效率之间的平衡，SpaiC设计采用神经科学风格的前端和深度学习后端结构设计。我们提供了广泛的示例，包括神经回路模拟，深入的SNN学习和神经形态应用，展示了简洁的编码样式和框架的广泛可用性。 Spaic是一个专用的基于SPIKE的人工智能计算平台，它将显着促进新模型，理论和应用的设计，原型和验证。具有用户友好，灵活和高性能，它将有助于加快神经形态计算研究的快速增长和广泛的适用性。

Event-based simulations of Spiking Neural Networks (SNNs) are fast and accurate. However, they are rarely used in the context of event-based gradient descent because their implementations on GPUs are difficult. Discretization with the forward Euler method is instead often used with gradient descent techniques but has the disadvantage of being computationally expensive. Moreover, the lack of precision of discretized simulations can create mismatches between the simulated models and analog neuromorphic hardware. In this work, we propose a new exact error-backpropagation through spikes method for SNNs, extending Fast \& Deep to multiple spikes per neuron. We show that our method can be efficiently implemented on GPUs in a fully event-based manner, making it fast to compute and precise enough for analog neuromorphic hardware. Compared to the original Fast \& Deep and the current state-of-the-art event-based gradient-descent algorithms, we demonstrate increased performance on several benchmark datasets with both feedforward and convolutional SNNs. In particular, we show that multi-spike SNNs can have advantages over single-spike networks in terms of convergence, sparsity, classification latency and sensitivity to the dead neuron problem.

超低功耗本地信号处理是始终安装在设备上的边缘应用的关键方面。尖刺神经网络的神经形态处理器显示出很大的计算能力，同时根据该领域的需要满足有限的电力预算。在这项工作中，我们提出了尖峰神经动力学作为扩张时间卷积的自然替代品。我们将这个想法扩展到WaveSense，这是一个由Wavenet Architects的激发灵感的尖峰神经网络。WaveSense使用简单的神经动力学，固定时间常数和简单的前馈结构，因此特别适用于神经形态实现。我们在几个数据集中测试此模型的功能，以用于关键字斑点。结果表明，该网络击败了其他尖刺神经网络的领域，并达到了诸如CNN和LSTM的人工神经网络的最先进的性能。

尖峰神经网络（SNN）已成为用于分类任务的硬件有效体系结构。基于尖峰的编码的惩罚是缺乏完全使用尖峰执行的通用训练机制。已经进行了几项尝试，用于采用在非加速人工神经网络（ANN）中使用的强大反向传播（BP）技术：（1）SNN可以通过外部计算的数值梯度来训练。 （2）基于天然尖峰的学习的主要进步是使用具有分阶段的前向/向后传递的尖峰时间依赖性可塑性（STDP）的近似反向传播。但是，在此类阶段之间的信息传输需要外部内存和计算访问。这是神经形态硬件实现的挑战。在本文中，我们提出了一种基于随机SNN的后式Prop（SSNN-BP）算法，该算法利用复合神经元同时计算前向通行激活，并用尖峰明确计算前向传递梯度。尽管签名的梯度值是基于SPIKE的表示的挑战，但我们通过将梯度信号分为正和负流来解决这一问题。复合神经元以随机尖峰传播的形式编码信息，并将反向传播的权重更新转换为时间和空间上局部离散的STDP类似STDP的Spike Concike更新，使其与硬件友好的电阻式处理单元（RPU）兼容。此外，我们的方法使用足够长的尖峰训练来接近BP ANN基线。最后，我们表明，可以通过强制执行胜利者的抑制性横向连接来实现软磁体交叉渗透损失函数。我们的SNN通过与MNIST，时尚和扩展的MNIST数据集的ANN相当的性能来表现出极好的概括。因此，SSNN-BP可以使BP与纯粹基于尖峰的神经形态硬件兼容。

Neuromorphic computing using biologically inspired Spiking Neural Networks (SNNs) is a promising solution to meet Energy-Throughput (ET) efficiency needed for edge computing devices. Neuromorphic hardware architectures that emulate SNNs in analog/mixed-signal domains have been proposed to achieve order-of-magnitude higher energy efficiency than all-digital architectures, however at the expense of limited scalability, susceptibility to noise, complex verification, and poor flexibility. On the other hand, state-of-the-art digital neuromorphic architectures focus either on achieving high energy efficiency (Joules/synaptic operation (SOP)) or throughput efficiency (SOPs/second/area), resulting in poor ET efficiency. In this work, we present THOR, an all-digital neuromorphic processor with a novel memory hierarchy and neuron update architecture that addresses both energy consumption and throughput bottlenecks. We implemented THOR in 28nm FDSOI CMOS technology and our post-layout results demonstrate an ET efficiency of 7.29G $\text{TSOP}^2/\text{mm}^2\text{Js}$ at 0.9V, 400 MHz, which represents a 3X improvement over state-of-the-art digital neuromorphic processors.